Fan-in leadframe semiconductor package

ABSTRACT

A semiconductor package comprising a plurality of elongate leads which each have opposed inner and outer ends, opposed first and second surfaces, and a third surface which is disposed in opposed relation to the first surface and recessed relative to the second surface. The second surface of each lead is positioned in close proximity to the inner end thereof. The third surface of each lead extends to the outer end thereof. A semiconductor die is attached to portions of the first surfaces of at least some of the leads. The semiconductor die is itself electrically connected to at least some of the leads. A package body covers the semiconductor die and the leads such that the second surfaces of the leads are exposed in a bottom surface of the package body and the outer ends of the leads are exposed in respective side surfaces of the package body.

CROSS-REFERENCE TO RELATED APPLICATIONS

Not Applicable

STATEMENT RE: FEDERALLY SPONSORED RESEARCH/DEVELOPMENT

Not Applicable

BACKGROUND OF THE INVENTION

The present invention relates generally to integrated circuit chip package technology and, more particularly, to a unique fan-in leadframe design for a semiconductor package which provides a reduced land footprint thus improving solder joint reliability, and further simplifies motherboard routing due to the availability of free space under the semiconductor package outside of the land pattern.

Integrated circuit or semiconductor dies are conventionally enclosed in plastic packages that provide protection from hostile environments and enable electrical interconnection between the semiconductor die and an underlying substrate such as a printed circuit board (PCB) or motherboard. The elements of such a package include a metal leadframe, a semiconductor die, bonding material to attach the semiconductor die to the leadframe, bond wires which electrically connect pads or terminals on the semiconductor die to individual leads of the leadframe, and a hard plastic encapsulant material which covers the other components and forms the exterior of the package often referred to as the package body.

The leadframe is the central supporting structure of such a semiconductor package. A portion of the leadframe is internal to the package, i.e., completely surrounded by the plastic encapsulant. Portions of the leads of the leadframe extend externally from the package or are partially exposed within the encapsulant material for use in electrically connecting the package to another component.

In certain semiconductor package designs, the bottom surface of each of the leads of the leadframe is exposed within the bottom surface of the package body formed by the hardening of the encapsulant material. In this design, solderable surfaces are provided on only the bottom surface of the package body and, more particularly, by the exposed bottom surfaces of the leads which are often referred to as lands. This type of semiconductor package is typically attached to the printed circuit board or motherboard by printing solder paste on the board, positioning the exposed bottom surfaces of the leads upon the solder paste, and completing a hot reflow process.

One major drawback associated with the above-described semiconductor package design is the relatively large land footprint which results in certain situations, such as when a large semiconductor die is integrated into the package. This increased land footprint causes increased stress in the solder joints during temperature cycling and further complicates motherboard routing due to the increased amount of space needed to accommodate the semiconductor package. The present invention eliminates this deficiency by providing a semiconductor package having a fan-in leadframe and adapted to accommodate a large semiconductor die. The fan-in semiconductor package of the present invention provides a reduced land footprint, thereby improving solder joint reliability due to a reduction in stress on solder joints during temperature cycling. The reduced land footprint also allows for easier motherboard routing due to free space being available under the semiconductor package outside of the land pattern. These, as well as other features and advantages of the present invention, will be discussed in more detail below.

BRIEF SUMMARY OF THE INVENTION

In accordance with the present invention, there is provided a semiconductor package having a uniquely configured fan-in leadframe which is adapted to allow the semiconductor package to have a reduced land footprint or pattern despite accommodating a large semiconductor die. The reduced land footprint of the semiconductor package attributable to the inclusion of the fan-in leadframe improves solder joint reliability by reducing stress on solder joints during temperature cycling. The reduced land footprint also provides easier motherboard routing due to the free space available under the semiconductor package outside of the land pattern.

The present invention is best understood by reference to the following detailed description when read in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

These, as well as other features of the present invention, will become more apparent upon reference to the drawings wherein:

FIG. 1 is a cross-sectional view of a fan-in semiconductor package constructed in accordance with a first embodiment of the present invention;

FIG. 2 is a partial bottom plan view of the fan-in leadframe integrated into the semiconductor package shown in FIG. 1;

FIG. 3 is a bottom plan view of a fan-in leadframe constructed in accordance with a second embodiment of the present invention and having a semiconductor die mounted thereto;

FIG. 4 is a cross-sectional view of a fan-in semiconductor package constructed in accordance with a third embodiment of the present invention; and

FIG. 5 is a partial bottom plan view of the fan-in leadframe integrated into semiconductor package shown in FIG. 4.

Common reference numerals are used throughout the drawings and detailed description to indicate like elements.

DETAILED DESCRIPTION OF THE INVENTION

Referring now to the drawings wherein the showings are for purposes of illustrating preferred embodiments of the present invention only, and not for purposes of limiting the same, FIG. 1 depicts a fan-in semiconductor package 10 constructed in accordance with a first embodiment of the present invention. The semiconductor package 10 comprises a fan-in leadframe 12, a partial bottom plan view of which is shown in FIG. 2. The leadframe 12 includes an outer frame 14 having a generally quadrangular (e.g., square, rectangular) configuration. In this regard, the outer frame 14 defines two pairs of opposed sides, with one such pair being labeled with the reference numerals 16 in FIG. 2. Due to the configuration of the outer frame 14, the pair of opposed sides 16 thereof extend in spaced, generally parallel relation to each other.

As further seen in FIG. 2, integrally connected to and extending inwardly from each of the opposed sides 16 of the outer frame 14 are a plurality of elongate leads 18. In this regard, the leads 18 are segregated into two sets, with the leads 18 of each such set being integrally connected to a respective one of the opposed sides 16. The leads 18 of each set are not of equal size, but rather are of at least two different lengths. Additionally, the leads 18 of each set are preferably arranged along a respective side 16 in a staggered pattern such that each adjacent pair of leads 18 of increased length has a lead 18 of decreased length therebetween as is shown in FIG. 2. The two sets of leads 18 are further arranged along the respective sides 16 of the outer frame 14 so that each lead 18 of increased length of one set extends in opposed relation to a lead 18 of increased length of the remaining set. Similarly, each lead 18 of reduced length of one set extends in opposed relation to a respective lead 18 of decreased length of the remaining set. As is further seen in FIG. 2, though the leads 18 of each set extend inwardly into the open interior of the outer frame 14, they are maintained in spaced relation to each other. In this regard, the opposed pairs of leads 18 of increased length are separated by identically sized gaps, with the opposed pairs of leads of decreased length also each being separated by identically sized gaps which are larger than those separating the opposed pairs of leads 18 of increased length.

As is shown in FIGS. 1 and 2, each of the leads 18 defines a generally planar first (top) surface 20 and an opposed, generally planar second (bottom) surface 22. In addition to the first and second surfaces 20, 22, each of the leads 18 defines a third surface 24 which is disposed in opposed relation to the first surface 20, but is perpendicularly offset or recessed relative to the second surface 22. As a result, as is best seen in FIG. 1, the thickness between the first and second surface 20, 22 of each lead 18 substantially exceeds the thickness between the first and third surfaces 20, 24 thereof. The leads 18 are also formed such that the area of increased thickness of each lead 18 (which defines the second surface 22 thereof) is disposed in close proximity to the distal end of such lead 18, the distal end being that end which is disposed furthest from the corresponding side 16 of the outer frame 14.

It is contemplated that the leadframe 12 will be fabricated from a conductive metal material (e.g., copper) through a mechanical stamping and/or chemical etching process. In this regard, the formation of the third surfaces 24 of the leads 18 preferably occurs as a result of the completion of a chemical etching process. As will be recognized, prior to any such chemical etching process, portions of each lead 18 are masked as needed to prevent any reduction in the original thickness thereof, such original thickness being reflected in the distance separating the first and second surfaces 20, 22 of each lead 18 from each other. As is further seen in FIG. 2, it is contemplated that each lead 18 may further be formed such that the width of the second surface 22 exceeds that of the third surface 24 thereof. However, those of ordinary skill in the art will recognize that the second and third surfaces 22, 24 of each lead 18 need not necessarily be formed to be of differing widths.

In addition to the leadframe 12, the semiconductor package 10 comprises a semiconductor die 26. As seen in FIG. 1, the semiconductor die 26 is attached to portions of the first surfaces 20 of at least some of the leads 18 of each of the first and second sets thereof. The attachment of the semiconductor die 26 to the first surfaces 20 of the leads 18 is preferably facilitated through the use of a suitable adhesive. Upon the mounting of the semiconductor die 26 to the leads 18 in the above-described manner, conductive wires 28 are used to electrically connect pads or terminals disposed on the top surface of the semiconductor die 26 to the first surfaces 20 of respective ones of the leads 18. Though not shown, it is contemplated that at least a portion of the first surface 20 of each of the leads 18 may include a layer of conductive plating formed thereon to assist in the adhesion and conductive connection of the conductive wire 28 to the corresponding lead 18.

Subsequent to the electrical connection of the semiconductor die 26 to the leads 18 through the use of the conductive wires 28, a plastic encapsulant material is applied to portions of the leadframe 12, the semiconductor die 26, and the conductive wires 28. The hardening of the encapsulant material facilitates the formation of a package body 30 of the semiconductor package 10. The package body 30 defines a generally planar top surface 32, an opposed, generally planar bottom surface 34, and a peripheral side surface 36 which extends generally perpendicularly relative to the bottom surface 34. In the semiconductor package 10, the second surfaces 22 of the leads 18 are exposed in and substantially flush with the bottom surface 34 of the package body 30. These exposed second surfaces 22 of the leads 18 define the “lands” and hence the land pattern or footprint of the semiconductor package 10. It is contemplated that each land defined by the second surface 22 of a respective lead 18 may include a layer of solderable plating 38 (e.g., NiPd, Matte Sn) applied thereto. Such layers of solderable plating 38 will typically be applied to the second surfaces 32 of the leads 18 subsequent to the complete formation of the package body 30.

It will be recognized that the complete formation of the semiconductor package 10 involves the singulation or severing of the outer frame 14 of the leadframe 12 from the remainder thereof. Such singulation occurs subsequent to the formation of the package body 30, and may be completed via a sawing or punching process. The singulation or removal of the outer frame 14 from the remainder of the leadframe 12 effectively electrically isolates the individual leads 18 from each other. As a result of the completion of the singulation process, each lead 18 defines an outer end which is exposed in and substantially flush with the side surface 36 of the package body 30, the third surface 24 extending to such outer end. Advantageously, the partial etching of the leads 18 as facilitates the formation of the third surfaces 24 thereof allows the encapsulant material which is used to form the package body 30 to underflow the leads 18 in a manner covering the third surfaces 24 thereof, thereby effectively locking the leads 18 to the package body 30.

Due to the configuration of each of the leads 18 of the semiconductor package 10 as described above, the land footprint of the semiconductor package 10 is significantly reduced in comparison to the land footprint which would result if the second surfaces 22 of the leads 18 were all located at or in very close proximity to the peripheral side surface 36 of the package body 30 in accordance with conventional semiconductor package designs. Signals transmitted from the semiconductor die 26 to the leads 18 via the conductive wires 28 are routed inwardly to the second surfaces 22 of the leads 18, and hence the lands defined thereby. As indicated above, the fan-in configuration of the leadframe 12 and hence the semiconductor package 10 results in improvements in solder joint reliability due to the reduced land footprint, and further allows for easier motherboard routing due to the free space available under the semiconductor package 10 outside of the land pattern defined by the second surfaces 22 of the leads 18.

Referring now to FIG. 3, there is shown a fan-in leadframe 40 constructed in accordance with a second embodiment of the present invention. The leadframe 40 includes an outer frame 42 having a generally quadrangular (e.g., square, rectangular) configuration. The outer frame 14 defines two pairs of opposed sides, with one such pair being labeled with the reference numerals 44 in FIG. 3, and the remaining pair being labeled with the reference numerals 46.

The leadframe 40 includes a generally quadrangular die pad 48 which resides within the interior of the outer frame 46. The die pad 48 is integrally connected to the sides 46 of the outer frame 42 by a plurality of tie bars 50 extending therebetween. Integrally connected to and extending inwardly from each of the opposed sides 44 of the outer frame 42 are a plurality of elongate leads 52. The leads 52 are segregated into two sets, with the leads 52 of each such set being integrally connected to a respective one of the opposed sides 44. The leads 52 of each set are of equal length. Though not required, the leads 52 are preferably arranged to extend inwardly into the open interior of the outer frame 42 such that each lead 52 of one set extends in opposed relation to a respective one of the leads 52 of the remaining set.

In the leadframe 40, the die pad 48 defines a generally planar first (top) surface and an opposed, generally planar second (bottom) surface 54. The die pad 48 is not formed to be of uniform thickness. Rather, the die pad 48 defines a third surface 60 which circumvents the second surface 54, and is perpendicularly offset or recessed relative to the second surface 54. As a result, the thickness between the first surface and the second surface 54 of the die pad 48 substantially exceeds the thickness between the first surface and the third surface 60 thereof.

Similarly, each of the leads 52 defines a generally planar first (top) surface and an opposed, generally planar second (bottom) surface 56. In addition to the first surface and second surface 56, each of the leads 52 defines a third surface 58 which is disposed in opposed relation to the first surface thereof, but is perpendicularly offset or recessed relative to the second surface 56. As a result, the thickness between the first surface and second surface 56 of each lead 52 substantially exceeds the thickness between the first surface and the third surface 58 thereof. The leads 52 are also formed such that the area of increased thickness of each lead 52 (which defines the second surface 56 thereof) extends to the distal end of such lead 52, the distal end being that end which is disposed furthest from the corresponding side 44 of the outer frame 42.

It is contemplated that the leadframe 40 will be fabricated from a conductive metal material (e.g, copper) through a mechanical stamping and/or chemical etching process. In this regard, the formation of the third surfaces 58 of the leads 52 and third surface 60 of the die pad 48 preferably occur as a result of the completion of a chemical etching process. As will be recognized, prior to any such chemical etching process, portions of each lead 52 and the die pad 48 are masked as needed to prevent any reduction in the original thickness thereof, such original thicknesses being reflected in the distance separating the first surface and second surface 56 of each lead 52 from each other, and the distance separating the first surface and the second surface 54 of the die pad 48 from each other. In the leadframe 40, the tie bars 50 used to secure the die pad 48 to the outer frame 42 are also subjected to the chemical etching process in a manner effectively decreasing the thickness thereof. In the fully etched leadframe 40, the second surfaces 56 of the leads 52 extend in generally co-planar relation to the second surface 54 of the die pad 48.

In FIG. 3, a semiconductor die 62 is shown as being mounted to the first surface of the die pad 48 and to portions of the first surfaces of at least some of the leads 52 of each of the first and second sets thereof. The attachment of the semiconductor die 62 to the die pad 48 and to the leads 52 is preferably facilitated through the use of a suitable adhesive. Upon the mounting of the semiconductor die 62 to the die pad 48 and leads 52 in the above-described manner, conductive wires are used to electrically connect pads or terminals disposed on the semiconductor die 62 to the first surfaces of respective ones of the leads 52. At least a portion of the first surface of each of the leads 52 may include a layer of conductive plating formed thereon to assist in the adhesion and conductive connection of these conductive wires to the corresponding leads 52.

Though not shown in FIG. 3, subsequent to the electrical connection of the semiconductor die 62 to the leads 52 through the use of the conductive wires, a plastic encapsulant material is applied to portions of the leadframe 40, the semiconductor die 62 and such conductive wires. As described above in relation to the semiconductor package 10, the hardening of such encapsulant material facilitates the formation of a package body. In the fully formed package body, the second surfaces 56 of the leads 52 will be exposed in and substantially flush with a bottom surface defined by such package body. Also exposed in and substantially flush with the bottom surface of such package body will be the bottom surface 54 of the die pad 48. The exposed second surfaces 56 of the leads 52 will define the lands and hence the land pattern or footprint of the semiconductor package including the leadframe 40.

It will be recognized that the complete formation of a semiconductor package including the leadframe 40 will involve the singulation or severing of the outer frame 42 of the leadframe 40 from the remainder thereof. The singulation or removal of the outer frame 42 from the remainder of the leadframe 40 effectively electrically isolates the leads 52 from each other. In the fully formed semiconductor package, the outer ends of the leads 52 formed as a result of the singulation or removal of the outer frame 42 will be exposed in and substantially flush with the side surface of the package body, the third surface 53 of each lead 52 extending to the outer end thereof. Similarly, the singulation process will result in the tie bars 50 of the leadframe 40 defining outer ends which are exposed in and substantially flush with the side surface of the package body. Advantageously, the partial etching of the leads 52 as facilitates the formation of the third surfaces 58 thereof allows the encapsulant material which is used to form the package body to underflow the leads 52 in a manner covering the third surfaces 58 thereof, thereby effectively locking the leads 52 to the package body. Similarly, the encapsulant material is able to underflow the peripheral portion of the die pad 48 in a manner covering the third surface 60, thereby further locking the die pad 48 to the package body. The configuration of the leads 52 in a semiconductor package constructed through the use of the leadframe 40 provides the same advantages described above in relation to the leads 18 of the semiconductor package 10.

It is contemplated that certain variations may be made to the leadframes 12, 40 without departing from the spirit and scope of the present invention. For example, the leads 18 of the leadframe 12 may alternatively be provided in equal lengths, with the leads 52 of the leadframe 40 alternatively being provided in differing lengths. Additionally, in the leadframe 12, it is contemplated that leads 18 of identical or differing lengths may be integrally connected to and extended inwardly from all four sides of the outer frame 14, rather than only the opposed sides 16 thereof. Similarly, in the leadframe 40, the leads 52 may be integrally connected to and extend inwardly from all of the sides 44, 46 of the outer frame 42, rather than from only the sides 44 thereof. In such alternative configuration, the die pad 48 may be supported within the interior of the outer frame 42 by tie bars which extend from respective corners of the die pad 48 to corresponding corners of the outer frame 42.

Referring now to FIG. 4, there is shown a fan-in semiconductor package 70 constructed in accordance with a third embodiment of the present invention. The semiconductor package 70 comprises a fan-in leadframe 72, a partial bottom plan view of which is shown in FIG. 5. The leadframe 72 includes an outer frame 74 having a generally quadrangular (e.g., square, rectangular) configuration. In this regard, the outer frame 74 defines two pairs of opposed sides, with one such pair being labeled with the reference numerals 76 in FIG. 5. Due to the configuration of the outer frame 74, the pair of opposed sides 76 thereof extend in spaced, generally parallel relation to each other.

Integrally connected to and extending inwardly from each of the opposed side 76 of the outer frame 74 are a plurality of elongate leads 78. The leads 78 are segregated into two sets, with the leads 78 of each such set being integrally connected to a respective one of the opposed sides 76. The leads 78 of each set are preferably of substantially equal length. The two sets of leads 78 are arranged along respective sides 76 of the outer frame 74 so that each lead 78 of one set extends in opposed relation to a lead 78 of the remaining set. The opposed pairs of the leads 78 are separated from each other by identically sized gaps.

As shown in FIGS. 4 and 5, each of the leads 78 defines a generally planar first (top) surface 80 and an opposed, generally planar second (bottom) surface 82. In addition to the first and second surfaces 80, 82, each of the leads 78 defines a third surface 84 which is disposed in opposed relation to the first surface 80, but is perpendicularly offset or recessed relative to the second surface 82. As a result, as is best seen in FIG. 4, the thickness between the first and second surfaces 80, 82 of each lead 78 substantially exceeds the thickness between the first and third surfaces 80, 84 thereof. The leads 78 are also formed such that the area of increased thickness of each lead 78 (which defines the second surface 82 thereof) is disposed in close proximity to the distal end of such lead 78, the distal end being that end which is disposed furthest from the corresponding side 76 of the outer frame 74.

Like the leadframe 12 described above, it is contemplated that the leadframe 72 will be fabricated from a conductive metal material (e.g., copper) through a mechanical stamping and/or chemical etching process. The formation of the third surfaces 84 of the leads 78 preferably occurs as a result of the completion of a chemical etching process. Prior to any such chemical etching process, portions of each lead 78 are masked as needed to prevent any reduction in the original thickness thereof, such original thickness being reflected in the distance separating the first and second surfaces 80, 82 of each lead 78 from each other. As further seen in FIG. 5, it is contemplated that each lead 78 may further be formed such that the width of the second surface 82 exceeds that of the third surface 84 thereof. However, those of ordinary skill in the art will recognize that the second and third surfaces 82, 84 of each lead 78 need not necessarily be formed to be of differing widths.

In addition to the leadframe 72, the semiconductor package 70 comprises a semiconductor die 86. As seen in FIG. 4, the semiconductor die 86 is attached to portions of the first surfaces 80 of at least some of the leads 78 of each of the first and second sets thereof. The attachment of the semiconductor die 86 to the first surfaces 80 of the leads 78 is preferably facilitated through the use of a suitable adhesive. Upon the mounting of the semiconductor die 86 to the leads 78 in the above-described manner, conductive wires 88 are used to electrically connect pads or terminals disposed on the top surface of the semiconductor die 86 to the first surfaces 80 of respective ones of the leads 78. Though not shown, it is contemplated that at least a portion of the first surface 80 of each of the leads 78 may include a layer of conductive plating formed thereon to assist in the adhesion and conductive connection of each conductive wire 88 to the corresponding lead 78.

Subsequent to the electrical connection of the semiconductor die 86 to the leads 78 through the use of the conductive wires 88, a plastic encapsulant material is applied to portions of the leadframe 72, the semiconductor die 86, and the conductive wires 88. The hardening of the encapsulant material facilitates the formation of a package body 90 of the semiconductor package 70. The package body 90 defines a generally planar top surface 92, an opposed, generally planar bottom surface 94, and a peripheral side surface 96 which extends generally perpendicularly relative to the bottom surface 94. In the semiconductor package 70, the second surfaces 82 of the leads 78 are exposed in and substantially flush with the bottom surface 94 of the package body 90. These exposed second surfaces 82 of the leads 78 define the “lands” and hence the land pattern or footprint of the semiconductor package 70. It is contemplated that each land defined by the second surface 82 of a respective lead 78 may include a layer of solder plating 98 applied thereto. Such layers of solder plating 98 will typically be applied to the second surfaces 82 of the leads 78 subsequent to the complete formation of the package body 90.

The complete formation of the semiconductor package 70 involves the singulation or severing of the outer frame 74 of the leadframe 72 from the remainder thereof. Such singulation occurs subsequent to the formation of the package body 90, and may be completed via a sawing or punching process. The singulation or removal of the outer frame 74 from the remainder of the leadframe 72 effectively electrically isolates the individual leads 78 from each other. As a result of the completion of the singulation process, each lead 78 defines an outer end which is exposed in and substantially flush with the side surface 96 of the package body 90, the third surface 84 extending to such outer end. The partial etching of the leads 78 as facilitates the formation of the third surfaces 84 thereof allows the encapsulant material which is used to form the package body 90 to underflow the leads 78 in a manner covering the third surfaces 84, thereby effectively locking the leads 78 to the package body 90.

Due to the configuration of each of the leads 78 of the semiconductor package 70, the land footprint of the semiconductor package 70 is significantly reduced in comparison to the land footprint which would result if the second surfaces 82 of the leads 78 were all located at or in very close proximity to the peripheral side surface 96 of the package body 90 in accordance with conventional semiconductor package designs. Signals transmitted from the semiconductor die 86 to the leads 78 via the conductive wires 88 are routed inwardly to the second surfaces 82 of the leads 78, and hence the lands defined thereby. The fan-in configuration of the leadframe 72 and hence the semiconductor package 70 results in improvements in solder joint reliability due to the reduced land footprint, and further allows for easier motherboard routing due to the free space available under the semiconductor package 70 outside of the land pattern defined by the second surfaces 82 of the leads 78.

This disclosure provides exemplary embodiments of the present invention. The scope of the present invention is not limited by these exemplary embodiments. Numerous variations, whether explicitly provided for by the specification or implied by the specification, such as variations in structure, dimension, type of material and manufacturing process may be implemented by one of skill in the art in view of this disclosure. 

1. A semiconductor package comprising: a plurality of elongate leads, each having: opposed inner and outer ends; a first surface; a second surface disposed in opposed relation to the first surface and positioned in close proximity to the inner end; and a third surface disposed in opposed relation to the first surface and recessed relative to the second surface, the third surface extending to the outer end; the leads being segregated into at least two sets, with the leads of each set being provided in only first and second differing lengths; a semiconductor die attached to portions of the first surfaces of each of the leads, the semiconductor die being electrically connected to at least some of the leads; and a package body covering the semiconductor die and the leads such that the second surfaces of the leads are exposed in a bottom surface of the package body and the outer ends of the leads are exposed in a side surface of the package body.
 2. The semiconductor package of claim 1 wherein the semiconductor die is electrically connected to the leads via conductive wires which extend from the semiconductor die to the first surfaces of at least some of the leads, the conductive wires being covered by the package body.
 3. The semiconductor package of claim 1 wherein the leads are segregated into only two sets which extend along respective ones of an opposed pair of sides of the semiconductor die.
 4. The semiconductor package of claim 1 wherein the leads of each set are arranged in a staggered pattern such that a lead of the first length is disposed between each adjacent pair of leads of the second length.
 5. The semiconductor package of claim 1 further comprising: a die pad defining opposed first and second surfaces; the semiconductor die being attached to at least a portion of the first surface of the die pad.
 6. The semiconductor package of claim 5 wherein the second surface of the die pad and the second surfaces of the leads extend in generally co-planar relation to each other.
 7. The semiconductor package of claim 5 wherein the die pad further comprises a third surface which circumvents the second surface thereof and is recessed relative thereto, the third surface of the die pad being covered by the package body.
 8. The semiconductor package of claim 1 wherein the second surface of each of the leads extends to the inner end thereof.
 9. A semiconductor package comprising: a plurality of elongate leads, each having: opposed inner and outer ends; a first surface; a second surface disposed in opposed relation to the first surface and positioned in close proximity to the inner end; and a third surface disposed in opposed relation to the first surface and recessed relative to the second surface, the third surface extending to the outer end; the leads being segregated into at least two sets, with the second surfaces of the leads of each set being arranged in a staggered pattern and the leads of each set being provided in only first and second differing lengths; a semiconductor die having a bottom surface attached to portions of the first surfaces of at least some of the leads wherein the attached to portions of the first surfaces completely overlie the second surfaces, the semiconductor die being electrically connected to at least some of the leads and overlying the entirety of the second surface of each of the leads; and a package body covering the semiconductor die and the leads such that the second surfaces of the leads are exposed in and substantially flush with a bottom surface of the package body; the leads being segregated into only two sets which extend along respective ones of an opposed pair of sides of the semiconductor die.
 10. The semiconductor package of claim 9 wherein the semiconductor die is electrically connected to the leads via conductive wires which extend from a top surface of the semiconductor die opposite the bottom surface to portions of the first surfaces of at least some of the leads which are disposed in opposed relation to the third surfaces thereof, the conductive wires being covered by the package body.
 11. A semiconductor package comprising: a plurality of elongate leads, each having: opposed inner and outer ends; a first surface; a second surface disposed in opposed relation to the first surface and positioned in close proximity to the inner end; and a third surface disposed in opposed relation to the first surface and recessed relative to the second surface, the third surface extending to the outer end; the leads being segregated into at least two sets, with the second surfaces of the leads of each set being arranged in a staggered pattern; a semiconductor die having a bottom surface attached to portions of the first surfaces of at least some of the leads wherein the attached to portions of the first surfaces completely overlie the second surfaces, the semiconductor die being electrically connected to at least some of the leads and overlying the entirety of the second surface of each of the leads; and a package body covering the semiconductor die and the leads such that the second surfaces of the leads are exposed in and substantially flush with a bottom surface of the package body; the leads of each set being provided in only first and second differing lengths and arranged in a staggered pattern such that a lead of the first length is disposed between each adjacent pair of leads of the second length.
 12. A semiconductor package comprising: a plurality of elongate leads, each having: opposed inner and outer ends; a first surface; a second surface disposed in opposed relation to the first surface and positioned in close proximity to the inner end; and a third surface disposed in opposed relation to the first surface and recessed relative to the second surface, the third surface extending to the outer end; the leads being segregated into at least two sets, with the leads of each set being provided in only first and second differing lengths and arranged in a staggered pattern such that a lead of the first length is disposed between each adjacent pair of leads of the second length and the second surfaces of the leads of the first length are offset relative to the second surfaces of the leads of the second length; a semiconductor die attached to portions of the first surfaces of at least some of the leads wherein the attached to portions of the first surfaces completely overlie the second surfaces, the semiconductor die being electrically connected to at least some of the leads and overlying the entirety of the second surface of each of the leads; and a package body covering the semiconductor die and the leads such that the second surfaces of the leads are exposed in a bottom surface of the package body and the outer ends of the leads are exposed in a slide surface of the package body.
 13. The semiconductor package of claim 12 wherein the semiconductor die is electrically connected to the leads via conductive wires which extend from the semiconductor die to the first surfaces of at least some of the leads, the conductive wires being covered by the package body.
 14. The semiconductor package of claim 12 wherein the leads are segregated into only two sets which extend along respective ones of an opposed pair of sides of the semiconductor die.
 15. The semiconductor package of claim 1 wherein the leads of each set are arranged in a staggered pattern such that each lead of the first length is disposed between an adjacent pair of leads of the second length and the second lead surfaces of the leads of the first length are offset relative to the second lead surfaces of the leads of the first length.
 16. The semiconductor package of claim 15 wherein the semiconductor die overlies the entirety of the second surface of each of the leads.
 17. The semiconductor package of claim 16 wherein the leads are segregated into only two sets which extend along respective ones of an opposed pair of sides of the semiconductor die.
 18. The semiconductor package of claim 4 wherein the second lead surfaces of the leads of the first length are offset relative to the second lead surfaces of the leads of the first length.
 19. The semiconductor package of claim 18 wherein the semiconductor die overlies the entirety of the second surface of each of the leads. 